1. Field of the Invention
Embodiments of the inventive concept relate to a thin film transistor array panel capable of increasing an aperture ratio and decreasing parasitic capacitance between a gate electrode and a drain electrode by reducing an area of a thin film transistor.
2. Description of the Related Art
A liquid crystal display (LCD) includes a liquid crystal layer interposed between two transparent substrates and drives the liquid crystal layer so as to adjust transmittance for each pixel, and thus a desired color can be displayed.
An LCD uses a variety of display modes in accordance with molecular arrangements in liquid crystals, and twisted nematic (TN) patterned vertical alignment (PVA), and electrically controlled birefringence (ECB) modes are often utilized because of advantages thereof in process. TN, PVA, and ECB LCDs are a vertical alignment (VA) mode in which liquid crystal molecules aligned parallel to a substrate shift to be aligned substantially perpendicular to the substrate when voltage is applied. Therefore, twisted nematic (TN), patterned vertical alignment (PVA) and electrically controlled birefringence (ECB) LCDs have disadvantageously a smaller viewing angle due to refractive index anisotropy of liquid crystal molecules when voltage is applied.
In order to overcome the disadvantage, LCDs in in-plane switching (IPS) and plane to line switching (PLS) modes have recently been developed.
A plane to line switching (PLS) mode LCD includes a first electrode and a second electrode with an insulating layer interposed therebetween in each pixel area and generates a fringe field so that all liquid crystal molecules between upper and lower substrates can move in each pixel area, thereby generating horizontal and vertical electric fields and improving an aperture ratio and transmittance.
A drain electrode of a thin film transistor is disposed in such a manner that a region where the drain electrode overlaps a gate electrode is different from a region where the drain electrode is in contact with a first electrode. In the plane to line switching (PLS) mode LCD, the insulating layer is further included to insulate the second electrode from the first electrode such that a contact hole through which the drain electrode is exposed has a larger area. As the contact hole through which the drain electrode is exposed becomes larger, the drain electrode also has an increasing area, which results in a lower aperture ratio.
Meanwhile, gate and source/drain parasitic capacitance (Cgs) occurring in an overlapping region of source and drain electrodes of a thin film transistor and a gate electrode acts to only lower data voltage (Vp) when gate voltage is changed from on-voltage to off-voltage. In this case, a lowering degree is referred to as kickback voltage (ΔVp).
Therefore, as the drain electrode has a larger area, parasitic capacitance between the gate electrode and the drain electrode increases, and thus kickback voltage (ΔVp) becomes higher. The high kickback voltage affects the first and second electrodes in a pixel, thereby increasing voltage ripple, such that image sticking occurs on a screen and, thus, resolution is lowered.
Accordingly, there is a demand for a structure that reduces an area of a thin film transistor and lowers parasitic capacitance between a gate electrode and a drain electrode.
It is to be understood that this background of the technology section is intended to provide useful background for understanding the here disclosed technology and as such, the technology background section may include ideas, concepts or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to corresponding effective filing dates of subject matter disclosed herein.